数字电路设计与嵌入式开发——组合逻辑电路的Verilog实现

module seven_seg_display (
    input [3:0] hexnum,          // 4-bit input, controls displayed data (0 to F)
    input [2:0] select,          // 3-bit input, selects which 7-segment display to control (000 to 101)
    output reg [5:0] led,        // 6-bit output, activates one of six 7-segment displays
    output reg [7:0] display        // 8-bit output, controls the segments of the 7-segment display
);

    // Control which 7-segment display is active based on the 'select' input
    always @(*) begin
        case (select)
            3'b000: led = 6'b000001; // Activate 7SD-1
            3'b001: led = 6'b000010; // Activate 7SD-2
            3'b010: led = 6'b000100; // Activate 7SD-3
            3'b011: led = 6'b001000; // Activate 7SD-4
            3'b100: led = 6'b010000; // Activate 7SD-5
            3'b101: led = 6'b100000; // Activate 7SD-6
            default: led = 6'b000000; // Turn off all displays for other values of 'select'
        endcase
    end

    // Determine the pattern to display on the 7-segment display based on 'hexnum'
    always @(*) begin
        case (hexnum)
            4'h0: display = 8'b11111100; // Display 0
            4'h1: display = 8'b01100000; // Display 1
            4'h2: display = 8'b11011010; // Display 2
            4'h3: display = 8'b11110010; // Display 3
            4'h4: display = 8'b01100110; // Display 4
            4'h5: display = 8'b10110110; // Display 5
            4'h6: display = 8'b10111110; // Display 6
            4'h7: display = 8'b11100000; // Display 7
            4'h8: display = 8'b11111110; // Display 8
            4'h9: display = 8'b11100110; // Display 9
            4'hA: display = 8'b11101110; // Display A
            4'hB: display = 8'b00111110; // Display B
            4'hC: display = 8'b10011100; // Display C
            4'hD: display = 8'b01111010; // Display D
            4'hE: display = 8'b10011110; // Display E
            4'hF: display = 8'b10001110; // Display F
            default: display = 8'b00000000; // Turn off all segments for invalid hexnum
        endcase
    end
endmodule

module Mux3to1_2bit (
    input [1:0] C,
    input [1:0] D0,
    input [1:0] D1,
    input [1:0] D2,
    output reg[1:0] Y
);
    always@(*)
    case (C)
        2'b00: Y = D0;
        2'b01: Y = D1;
        2'b10: Y = D2;
        default: Y = 2'b00;
    endcase
endmodule

module decoder3to8(
 input [2:0] in, // 3-bit input
 output reg [7:0] out // 8-bit output
);
    always @(*) begin
        out = 8'b0000_0000; // 初始化输出
        case (in)
            3'b000: out  = 8'b0000_0001;
            3'b001: out  = 8'b0000_0010;
            3'b010: out  = 8'b0000_0100;
            3'b011: out  = 8'b0000_1000;
            3'b100: out  = 8'b0001_0000;
            3'b101: out  = 8'b0010_0000;
            3'b110: out  = 8'b0100_0000;
            3'b111: out  = 8'b1000_0000;
            default: out = 8'b0000_0000;
        endcase
    end
endmodule

module encoder8to3(
 input [7:0] in, // 8-bit input
 output reg [2:0] out // 3-bit output
);
    always @(*) begin
        case (in)
            8'b0000_0001: out = 3'b000;
            8'b0000_0010: out = 3'b001;
            8'b0000_0100: out = 3'b010;
            8'b0000_1000: out = 3'b011;
            8'b0001_0000: out = 3'b100;
            8'b0010_0000: out = 3'b101;
            8'b0100_0000: out = 3'b110;
            8'b1000_0000: out = 3'b111;
            default: out      = 3'b000;
        endcase
    end
endmodule

module AdderSubtractor(
    input [2:0] A,    // 3-bit operand A
    input [2:0] B,    // 3-bit operand B
    input X,          // Control signal: 0 for addition, 1 for subtraction
    output [3:0] Y,   // 4-bit result to include overflow
    output Overflow   // Overflow indicator
);
    // 4-bit complement of A and B
    wire [3:0] A_comp;
    wire [3:0] B_comp;
    assign A_comp = {1'b0, A};
    assign B_comp = (X == 0) ? {1'b0, B} : {1'b1, ~B} + 1；
    assign Y = A_comp + B_comp;
    assign Overflow = (X == 0) ? Y[3] : 0;
endmodule